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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:10:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:10:13 -0700 |
| commit | afcb86c3d143c95643855da1159b0f245f75262c (patch) | |
| tree | 2b68ab15c9c9bca7b85292203206a905172173c7 | |
| parent | 0391499e46cd69cf809fe911fa7798b1ae994540 (diff) | |
| download | yosys-afcb86c3d143c95643855da1159b0f245f75262c.tar.gz yosys-afcb86c3d143c95643855da1159b0f245f75262c.tar.bz2 yosys-afcb86c3d143c95643855da1159b0f245f75262c.zip | |
abc9 to call "setundef -zero" behaving as for abc
| -rw-r--r-- | passes/techmap/abc9.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index edc07092b..3c4919b1f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -403,6 +403,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); + // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero + Pass::call(design, "setundef -zero"); + Pass::call(design, "aigmap"); handle_loops(design); |