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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 16:29:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 16:29:14 -0700 |
| commit | 88d43a519bd0ea9657baba8bf9bc6a845b6cf14d (patch) | |
| tree | 9f5068d43f6c4e2d9c159c5bb8867e89265a64d1 | |
| parent | 686e772f0bb3129e7d6469dc25548497f107ebc5 (diff) | |
| download | yosys-88d43a519bd0ea9657baba8bf9bc6a845b6cf14d.tar.gz yosys-88d43a519bd0ea9657baba8bf9bc6a845b6cf14d.tar.bz2 yosys-88d43a519bd0ea9657baba8bf9bc6a845b6cf14d.zip | |
Use -map instead of -symbols for aiger
| -rw-r--r-- | passes/techmap/abc9.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ec4a28d08..17d082833 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.aig; ", tempdir_name.c_str(), tempdir_name.c_str())); design->selection_stack.pop_back(); @@ -523,7 +523,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri bool builtin_lib = liberty_file.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); - AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */); + buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); + AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); reader.parse_xaiger(); ifs.close(); |