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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-15 12:22:05 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-15 12:22:05 -0700 |
| commit | 18a40458588f04bf7a3d30fde8fead95cee00dee (patch) | |
| tree | da23af7c69738e043e7cd4cceb15c050956578b9 | |
| parent | db1a5ec6a2a437b296e7ba9de78afaf3b440327f (diff) | |
| parent | 6323e73cc94627125a275b22b0b8ea290e750bc3 (diff) | |
| download | yosys-18a40458588f04bf7a3d30fde8fead95cee00dee.tar.gz yosys-18a40458588f04bf7a3d30fde8fead95cee00dee.tar.bz2 yosys-18a40458588f04bf7a3d30fde8fead95cee00dee.zip | |
Merge pull request #936 from YosysHQ/README-fix-quotes
README: fix some incorrect quoting
| -rw-r--r-- | README.md | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -312,10 +312,10 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. -- The ``dynports'' attribute is used by the Verilog front-end to mark modules +- The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- The ``hdlname'' attribute is used by some passes to document the original +- The ``hdlname`` attribute is used by some passes to document the original (HDL) name of a module when renaming a module. - The ``keep`` attribute on cells and wires is used to mark objects that should |