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* Merge pull request #1085 from YosysHQ/eddie/shregmap_improveEddie Hung2019-06-213-3/+129
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| * Actually, there might not be any harm in updating sigmap...Eddie Hung2019-06-201-3/+1
| * Add comment as per @cliffordwolfEddie Hung2019-06-201-0/+11
| * Add shregmap -tech xilinx testEddie Hung2019-06-122-2/+63
| * Revert "Try way that doesn't involve creating a new wire"Eddie Hung2019-06-111-15/+10
| * Try way that doesn't involve creating a new wireEddie Hung2019-06-111-10/+15
| * If d_bit already in sigbit_chain_next, create extra wireEddie Hung2019-06-101-3/+6
| * Add testEddie Hung2019-06-102-0/+53
* | Merge pull request #1122 from YosysHQ/clifford/jsonportsClifford Wolf2019-06-212-0/+16
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| * | Added JSON upto and offsetClifford Wolf2019-06-212-0/+16
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* | Merge pull request #1121 from YosysHQ/ecp5-ccu2c-invClifford Wolf2019-06-211-4/+5
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| * | ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
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* | Merge pull request #1117 from bwidawsk/more-homeClifford Wolf2019-06-212-0/+5
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| * | Add a few more filename rewritesBen Widawsky2019-06-202-0/+5
* | | Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-212-0/+12
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| * | | Add testEddie Hung2019-06-201-0/+11
| * | | Make genvar a signed typeEddie Hung2019-06-201-0/+1
* | | | Merge pull request #1116 from YosysHQ/eddie/fix1115Clifford Wolf2019-06-213-7/+41
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| * | | | Add CHANGELOG entryEddie Hung2019-06-201-1/+2
| * | | | Extend sign extension testsEddie Hung2019-06-201-4/+16
| * | | | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
| * | | | Revert "Fix sign extension when sign is 1'bx"Eddie Hung2019-06-201-1/+1
| * | | | Remove leftover commentEddie Hung2019-06-201-3/+0
| * | | | Add testEddie Hung2019-06-201-0/+24
| * | | | Fix sign extension when sign is 1'bxEddie Hung2019-06-201-1/+1
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* / / / Fix gcc invalidation behaviour for write_aigerEddie Hung2019-06-201-1/+2
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* | | Fix typo, fixes #1095Clifford Wolf2019-06-201-1/+1
* | | Improve shregmap help message, fixes #1113Clifford Wolf2019-06-201-0/+2
* | | Update some .gitignore filesClifford Wolf2019-06-202-3/+3
* | | Fix typoClifford Wolf2019-06-201-2/+2
* | | Merge branch 'towoe-unpacked_arrays'Clifford Wolf2019-06-202-1/+23
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| * | Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| * | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...Clifford Wolf2019-06-203-1/+13
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| * | Unpacked array declaration using sizeTobias Wölfel2019-06-193-1/+13
* | | Merge pull request #1111 from acw1251/help_summary_fixesEddie Hung2019-06-194-6/+6
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| * | | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
| * | | Fixed the help summary line for a few commandsacw12512019-06-194-6/+6
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* | | Fix bug in #1078, add entry to CHANGELOGEddie Hung2019-06-192-3/+4
* | | Merge pull request #1109 from YosysHQ/clifford/fix1106Clifford Wolf2019-06-196-9/+48
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| * | | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-196-9/+48
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* | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-195-16/+92
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| * | | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| * | | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| * | | Add defaultvalue attributeClifford Wolf2019-06-192-0/+15
| * | | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
* | | | Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
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* | | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-195-0/+8
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| * | | Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| * | | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
* | | | Merge pull request #1104 from whitequark/case-semanticsClifford Wolf2019-06-192-1/+40
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