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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:03:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:03:05 -0700 |
| commit | e63324f5ef2ebb14fa0cc88544f577406f95b223 (patch) | |
| tree | a59a918a0a4cb047917a3cda91c84d08a851a815 | |
| parent | 9c61fb0e0c23f00bacf316f7efd358c66f2f6397 (diff) | |
| download | yosys-e63324f5ef2ebb14fa0cc88544f577406f95b223.tar.gz yosys-e63324f5ef2ebb14fa0cc88544f577406f95b223.tar.bz2 yosys-e63324f5ef2ebb14fa0cc88544f577406f95b223.zip | |
Actually, there might not be any harm in updating sigmap...
| -rw-r--r-- | passes/techmap/shregmap.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 8881ba468..d9d1e257b 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -304,11 +304,9 @@ struct ShregmapWorker // so that it can be identified as another chain // (omitting this common flop) // Link: https://github.com/YosysHQ/yosys/pull/1085 - // NB: This relies on us not updating sigmap with this - // alias otherwise it would think they are the same - // wire Wire *wire = module->addWire(NEW_ID); module->connect(wire, d_bit); + sigmap.add(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); } |