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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-10 16:16:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-10 16:16:40 -0700 |
| commit | f19aa8d989df9e443d26cf6beaf389c2f3d6a424 (patch) | |
| tree | 8d420acfd1b1f42b034ae5a8606d430811e6d0fa | |
| parent | c314ca3c51579a9c5305cbf9a69635e123db0423 (diff) | |
| download | yosys-f19aa8d989df9e443d26cf6beaf389c2f3d6a424.tar.gz yosys-f19aa8d989df9e443d26cf6beaf389c2f3d6a424.tar.bz2 yosys-f19aa8d989df9e443d26cf6beaf389c2f3d6a424.zip | |
If d_bit already in sigbit_chain_next, create extra wire
| -rw-r--r-- | passes/techmap/shregmap.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 21dfe9619..46f6a79fb 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -293,10 +293,13 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - if (sigbit_chain_next.count(d_bit)) { + auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; |