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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-21 10:13:13 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-21 10:13:13 +0200 |
| commit | 78e7a6f6f25c57ba560613f978ef8d9281fb615a (patch) | |
| tree | e35dfe61cad3b9f1cd44ef80e5a8336d69dcd005 | |
| parent | 86a753cc18f4e85449a93042298a8e4a617c674a (diff) | |
| parent | c20adc52638b0f3ba3b1c39e5286ae92e901005d (diff) | |
| download | yosys-78e7a6f6f25c57ba560613f978ef8d9281fb615a.tar.gz yosys-78e7a6f6f25c57ba560613f978ef8d9281fb615a.tar.bz2 yosys-78e7a6f6f25c57ba560613f978ef8d9281fb615a.zip | |
Merge pull request #1119 from YosysHQ/eddie/fix1118
Make genvar a signed type
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 | ||||
| -rw-r--r-- | tests/simple/generate.v | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4895d0302..d89b2dc88 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -517,6 +517,7 @@ wire_type_token: TOK_GENVAR { astbuf3->type = AST_GENVAR; astbuf3->is_reg = true; + astbuf3->is_signed = true; astbuf3->range_left = 31; astbuf3->range_right = 0; } | diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 3c55682cb..0e353ad9b 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -148,3 +148,14 @@ generate endgenerate assign out = steps[WIDTH].outer[0].val; endmodule + +// ------------------------------------------ + +module gen_test6(output [3:0] o); +generate + genvar i; + for (i = 3; i >= 0; i = i-1) begin + assign o[i] = 1'b0; + end +endgenerate +endmodule |