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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-20 12:06:58 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-20 12:06:58 +0200 |
| commit | 7f1461d64b3b4db44b627429ca422acfbcbb6809 (patch) | |
| tree | 577eadad515a8a0e02c686d1907b60f8c7621210 | |
| parent | 3b1e5264d8e333937fa9c06075b092bfd27be317 (diff) | |
| parent | 6a6dd5e0575950174e3abde7a13a3e3be73e5299 (diff) | |
| download | yosys-7f1461d64b3b4db44b627429ca422acfbcbb6809.tar.gz yosys-7f1461d64b3b4db44b627429ca422acfbcbb6809.tar.bz2 yosys-7f1461d64b3b4db44b627429ca422acfbcbb6809.zip | |
Merge branch 'towoe-unpacked_arrays'
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 8 | ||||
| -rw-r--r-- | tests/simple/arrays02.sv | 16 |
2 files changed, 23 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8234479cc..4895d0302 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1400,7 +1400,13 @@ wire_name: node->children.push_back(rng); } node->type = AST_MEMORY; - node->children.push_back($2); + auto *rangeNode = $2; + if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { + // SV array size [n], rewrite as [n-1:0] + rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); + rangeNode->children.push_back(AstNode::mkconst_int(0, false)); + } + node->children.push_back(rangeNode); } if (current_function_or_task == NULL) { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { diff --git a/tests/simple/arrays02.sv b/tests/simple/arrays02.sv new file mode 100644 index 000000000..76c2a7388 --- /dev/null +++ b/tests/simple/arrays02.sv @@ -0,0 +1,16 @@ +module uut_arrays02(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [16]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule |