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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-21 15:07:39 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-21 15:07:39 +0200 |
| commit | f0955452aecb528db4931d3a1844637e0f3f4cef (patch) | |
| tree | 7cd55382fc5a9b79ccd61ed0d02e78bb76692094 | |
| parent | c9949dba9994aa8289333657a52ef892c6e769d0 (diff) | |
| parent | a0d3d2bb41cd11b5b33620e16cb67c6568b16847 (diff) | |
| download | yosys-f0955452aecb528db4931d3a1844637e0f3f4cef.tar.gz yosys-f0955452aecb528db4931d3a1844637e0f3f4cef.tar.bz2 yosys-f0955452aecb528db4931d3a1844637e0f3f4cef.zip | |
Merge pull request #1121 from YosysHQ/ecp5-ccu2c-inv
ecp5: Improve mapping of $alu when BI is used
| -rw-r--r-- | techlibs/ecp5/arith_map.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index eb7947601..17bde0497 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -50,20 +50,21 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH2-1:0] AA = A_buf; wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH2-1:0] BX = B_buf; wire [Y_WIDTH2-1:0] C = {CO, CI}; wire [Y_WIDTH2-1:0] FCO, Y1; genvar i; generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice CCU2C #( - .INIT0(16'b0110011010101010), - .INIT1(16'b0110011010101010), + .INIT0(16'b1001011010101010), + .INIT1(16'b1001011010101010), .INJECT1_0("NO"), .INJECT1_1("NO") ) ccu2c_i ( .CIN(C[i]), - .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), - .A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1), .S0(Y[i]), .S1(Y1[i]), .COUT(FCO[i]) ); |