| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
| * | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 |
| * | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 |
| * | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
| * | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
| * | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 9 | -3/+93 |
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| | * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 4 | -50/+38 |
| | * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 10 | -5/+107 |
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| | | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 10 | -5/+107 |
| * | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 |
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| * | | Merge branch 'tux3-implicit_named_connection' | Clifford Wolf | 2019-06-07 | 4 | -3/+40 |
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| | * | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 3 | -13/+2 |
| | * | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int... | Clifford Wolf | 2019-06-07 | 5 | -4/+52 |
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| | | * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 5 | -12/+59 |
| * | | | | Merge pull request #1076 from thasti/centos7-build-fix | Clifford Wolf | 2019-06-07 | 1 | -1/+0 |
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| | * | | | remove boost/log/exceptions.hpp from wrapper generator | Stefan Biereigel | 2019-06-07 | 1 | -1/+0 |
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| * | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 14 | -10/+279 |
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| | * | | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 |
| | * | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ... | Maciej Kurc | 2019-06-04 | 4 | -0/+46 |
| | * | | | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 |
| | * | | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 |
| * | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iob | David Shah | 2019-06-06 | 1 | -0/+15 |
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| | * | | | | ECP5: implement all Diamond I/O buffer primitives. | whitequark | 2019-06-06 | 1 | -0/+15 |
| * | | | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 |
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| | * | | | | | Fix typo in opt_rmdff | Eddie Hung | 2019-06-05 | 1 | -2/+2 |
| * | | | | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069 | Clifford Wolf | 2019-06-06 | 1 | -0/+5 |
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| | * | | | | | | Error out if no top module given before 'sim' | Eddie Hung | 2019-06-05 | 1 | -0/+5 |
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| * / / / / / | Missing doc for -tech xilinx in shregmap | Eddie Hung | 2019-06-05 | 1 | -0/+3 |
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| * | | | | | Merge pull request #1067 from YosysHQ/clifford/fix1065 | Eddie Hung | 2019-06-05 | 1 | -1/+1 |
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| | * | | | | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065 | Clifford Wolf | 2019-06-05 | 1 | -1/+1 |
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| * | | | | | Merge pull request #1066 from YosysHQ/clifford/fix1056 | Clifford Wolf | 2019-06-05 | 1 | -1/+0 |
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| | * | | | | | Remove yosys_banner() from python wrapper init, fixes #1056 | Clifford Wolf | 2019-06-05 | 1 | -1/+0 |
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| * | | | | | Major rewrite of wire selection in setundef -init | Clifford Wolf | 2019-06-05 | 1 | -30/+89 |
| * | | | | | Indent fix | Clifford Wolf | 2019-06-05 | 1 | -23/+25 |
| * | | | | | Merge pull request #999 from jakobwenzel/setundefInitFix | Clifford Wolf | 2019-06-05 | 1 | -16/+23 |
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| | * | | | | | initialize more registers in setundef -init | Jakob Wenzel | 2019-05-09 | 1 | -16/+23 |
| * | | | | | | Fix typo in fmcombine log message, fixes #1063 | Clifford Wolf | 2019-06-05 | 1 | -2/+2 |
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| * | | | | | Merge pull request #1062 from tux3/patch-1 | Clifford Wolf | 2019-06-04 | 1 | -1/+1 |
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| | * | | | | | README.md: Missing formatting for <tag> | Tux3 | 2019-06-04 | 1 | -1/+1 |
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| * | | | | | Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map | Eddie Hung | 2019-06-03 | 1 | -6/+5 |
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| | * | | | | | Remove extra newline | Eddie Hung | 2019-06-03 | 1 | -1/+0 |
| | * | | | | | Execute techmap and arith_map simultaneously | Eddie Hung | 2019-06-03 | 1 | -6/+6 |
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| * | | / / | Only support Symbiotic EDA flavored Verific | Clifford Wolf | 2019-06-02 | 1 | -0/+8 |
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| * | | | | Fix "tee" handling of log_streams | Clifford Wolf | 2019-05-31 | 1 | -0/+5 |
| * | | | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ... | Clifford Wolf | 2019-05-30 | 1 | -0/+3 |
| * | | | | Merge pull request #1057 from mmicko/fix_478 | Clifford Wolf | 2019-05-30 | 1 | -0/+4 |
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| | * | | | | Aded one more load of .conf to support change of prefix | Miodrag Milanovic | 2019-05-29 | 1 | -0/+4 |
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| * | | | | Merge pull request #1049 from YosysHQ/clifford/fix1047 | Clifford Wolf | 2019-05-28 | 2 | -4/+15 |
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| | * | | | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 | Clifford Wolf | 2019-05-28 | 2 | -4/+15 |
| * | | | | | Merge pull request #1050 from YosysHQ/clifford/wandwor | Clifford Wolf | 2019-05-28 | 9 | -40/+207 |
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