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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-06 06:50:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-06 06:50:12 +0200 |
| commit | e4e1cd693055b9eaef20953603fd1793a3feb263 (patch) | |
| tree | d20a2fe90d783a464370ddf1db622eb03c496681 | |
| parent | 50e2dce5e7b9a193eab90def9b68e4d77b3789ca (diff) | |
| parent | feb2ddb52bd7ca590596e22f73a5d3c153907391 (diff) | |
| download | yosys-e4e1cd693055b9eaef20953603fd1793a3feb263.tar.gz yosys-e4e1cd693055b9eaef20953603fd1793a3feb263.tar.bz2 yosys-e4e1cd693055b9eaef20953603fd1793a3feb263.zip | |
Merge pull request #1071 from YosysHQ/eddie/fix_1070
Fix typo in opt_rmdff causing register to be incorrectly removed
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 2abffa2a9..eeb992a3e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -292,8 +292,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_q = dff->getPort("\\Q"); sig_c = dff->getPort("\\C"); sig_e = dff->getPort("\\E"); - val_cp = RTLIL::Const(dff->type[6] == 'P', 1); - val_ep = RTLIL::Const(dff->type[7] == 'P', 1); + val_cp = RTLIL::Const(dff->type[7] == 'P', 1); + val_ep = RTLIL::Const(dff->type[8] == 'P', 1); } else if (dff->type == "$ff") { sig_d = dff->getPort("\\D"); |