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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 14:16:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 14:16:24 -0700 |
| commit | dd134914cc93f7506504ad95aad438a468bb0fe8 (patch) | |
| tree | 990f882ea4b338c6b92763c1a4e24dd43e853042 | |
| parent | a3a80b755cb78866060f71348e2a0b14f96c574b (diff) | |
| download | yosys-dd134914cc93f7506504ad95aad438a468bb0fe8.tar.gz yosys-dd134914cc93f7506504ad95aad438a468bb0fe8.tar.bz2 yosys-dd134914cc93f7506504ad95aad438a468bb0fe8.zip | |
Error out if no top module given before 'sim'
| -rw-r--r-- | passes/sat/sim.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 53e248adf..4c3022c70 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -88,6 +88,8 @@ struct SimInstance SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) : shared(shared), module(module), instance(instance), parent(parent), sigmap(module) { + log_assert(module); + if (parent) { log_assert(parent->children.count(instance) == 0); parent->children[instance] = this; @@ -848,6 +850,9 @@ struct SimPass : public Pass { if (design->full_selection()) { top_mod = design->top_module(); + + if (!top_mod) + log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n"); } else { auto mods = design->selected_whole_modules(); if (GetSize(mods) != 1) |