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authorClifford Wolf <clifford@clifford.at>2019-05-28 19:02:26 +0200
committerGitHub <noreply@github.com>2019-05-28 19:02:26 +0200
commit349c47250a9779bc58634870d2e3facfe95fbff8 (patch)
tree19e10d852edaafe47622ba570dff5d5053246c81
parent8e647901ef6ea484bfe41628f258c53590ae4114 (diff)
parentcb285e4b87112779efe84a7b6c5ae4a76a69ae01 (diff)
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Merge pull request #1049 from YosysHQ/clifford/fix1047
Do not use shiftmul peepopt pattern when mul result is truncated
-rw-r--r--passes/pmgen/peepopt_shiftmul.pmg15
-rw-r--r--tests/simple/peepopt.v4
2 files changed, 15 insertions, 4 deletions
diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg
index fe861b728..6adab4e5f 100644
--- a/passes/pmgen/peepopt_shiftmul.pmg
+++ b/passes/pmgen/peepopt_shiftmul.pmg
@@ -1,4 +1,7 @@
pattern shiftmul
+//
+// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
+//
state <SigSpec> shamt
@@ -49,12 +52,16 @@ code
if (GetSize(port(shift, \Y)) > const_factor)
reject;
+ int factor_bits = ceil_log2(const_factor);
+ SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
+
+ if (GetSize(shamt) < factor_bits+GetSize(mul_din))
+ reject;
+
did_something = true;
log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
- int new_const_factor_log2 = ceil_log2(const_factor);
- int new_const_factor = 1 << new_const_factor_log2;
-
+ int new_const_factor = 1 << factor_bits;
SigSpec padding(State::Sx, new_const_factor-const_factor);
SigSpec old_a = port(shift, \A), new_a;
int trunc = 0;
@@ -73,7 +80,7 @@ code
if (trunc > 0)
new_a.remove(GetSize(new_a)-trunc, trunc);
- SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)};
+ SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
if (param(shift, \B_SIGNED).as_bool())
new_b.append(State::S0);
diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
index b27b9fe57..1bf427897 100644
--- a/tests/simple/peepopt.v
+++ b/tests/simple/peepopt.v
@@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in
assign o = i[s*W+:W];
endmodule
+module peepopt_shiftmul_1 (output y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+
module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
wire [3:0] t;
assign t = i * 3;