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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-07 11:46:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-07 11:46:16 +0200 |
| commit | a0b57f2a6ffae3b5770e38bf5a9af0df50db8522 (patch) | |
| tree | 1d33caae227f8a16bb66a7a0b021768bcfa97f42 | |
| parent | b637b3109d61ff2d120978975a7b8cdc2ca3f418 (diff) | |
| download | yosys-a0b57f2a6ffae3b5770e38bf5a9af0df50db8522.tar.gz yosys-a0b57f2a6ffae3b5770e38bf5a9af0df50db8522.tar.bz2 yosys-a0b57f2a6ffae3b5770e38bf5a9af0df50db8522.zip | |
Cleanup tux3-implicit_named_connection
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 | ||||
| -rw-r--r-- | tests/simple/implicit_ports.sv (renamed from tests/various/implicit_ports.sv) | 5 | ||||
| -rw-r--r-- | tests/various/implicit_ports.ys | 8 |
3 files changed, 2 insertions, 13 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 2fffc7536..6d3afed0e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -154,7 +154,7 @@ struct specify_rise_fall { %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list named_port +%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id %type <boolean> opt_signed opt_property unique_case_attr %type <al> attr case_attr diff --git a/tests/various/implicit_ports.sv b/tests/simple/implicit_ports.sv index 6a766bd51..8b0a6f386 100644 --- a/tests/various/implicit_ports.sv +++ b/tests/simple/implicit_ports.sv @@ -4,10 +4,8 @@ module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] r assign result = a + b; endmodule -module named_ports(output [2:0] alu_result, output cout); - wire [2:0] a = 3'b010, b = 3'b100; +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); wire cin = 1; - alu alu ( .a(a), .b, // Implicit connection is equivalent to .b(b) @@ -16,4 +14,3 @@ module named_ports(output [2:0] alu_result, output cout); .result(alu_result) ); endmodule - diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys deleted file mode 100644 index 7b4764921..000000000 --- a/tests/various/implicit_ports.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog -sv implicit_ports.sv -proc; opt - -flatten -select -module named_ports - -sat -verify -prove alu_result 6 -sat -verify -set-all-undef cout |