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| author | Tux3 <tux3@users.noreply.github.com> | 2019-06-04 10:45:41 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-04 10:45:41 +0200 |
| commit | c66d644b66f13d5cc54c78051bf97c0143d9940e (patch) | |
| tree | 49c5868f2fceee64610d53396432def3dd45783b | |
| parent | 1217e47e83d099561fed933208621d0402cf0972 (diff) | |
| download | yosys-c66d644b66f13d5cc54c78051bf97c0143d9940e.tar.gz yosys-c66d644b66f13d5cc54c78051bf97c0143d9940e.tar.bz2 yosys-c66d644b66f13d5cc54c78051bf97c0143d9940e.zip | |
README.md: Missing formatting for <tag>
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -413,7 +413,7 @@ Verilog Attributes and non-standard features $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant - expressions as <size>. If the expression is not a simple identifier, it + expressions as ``<size>``. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in |