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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
* xaiger: do not treat (* init=1'bx *) as 1'b0Eddie Hung2020-05-141-1/+1
* abc9: cleanupEddie Hung2020-05-141-4/+1
* abc9_ops: do not use (* abc9_init *)Eddie Hung2020-05-141-16/+31
* aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
* xaiger: when -dff use (* init *) for initial stateEddie Hung2020-05-141-3/+15
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-149-635/+398
* abc9: fix behaviour and help for -box optionEddie Hung2020-05-141-3/+7
* aiger: -xaiger to read $_DFF_[NP]_ back with new clocks createdEddie Hung2020-05-142-3/+24
* xaiger: output $_DFF_[NP]_ with mergeability if -dff optionEddie Hung2020-05-141-42/+44
* Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-146-1/+107
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| * test: add another testcase as per @nakengelhardtEddie Hung2020-05-141-0/+25
| * verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| * tests: update/extend task argument testsEddie Hung2020-05-132-2/+35
| * verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
| * tests: add #2042 testcaseEddie Hung2020-05-111-0/+12
| * Setup tests/verilog properlyEddie Hung2020-05-113-0/+24
* | Merge pull request #2052 from YosysHQ/claire/verific_memfixClaire Wolf2020-05-141-2/+12
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| * | Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
* | | Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixesClaire Wolf2020-05-142-12/+32
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| * | | opt_clean: improve warning messageEddie Hung2020-05-142-2/+2
| * | | opt_clean: add init testEddie Hung2020-05-141-0/+13
| * | | opt_clean: rminit without -purge; also remove if consistent with const..Eddie Hung2020-05-141-9/+17
| * | | opt_clean: really make 'clean' identical to 'opt_clean' by rminit tooEddie Hung2020-05-141-3/+2
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* | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-144-8/+35
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| * | techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-053-8/+30
| * | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
| * | test: add failing testEddie Hung2020-05-041-0/+5
* | | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
* | | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
* | | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
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* | Merge pull request #2038 from nakengelhardt/no-libdir-flagClaire Wolf2020-05-081-2/+1
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| * | Remove yosys libdir from LDFLAGS (and fix a typo)N. Engelhardt2020-05-071-2/+1
* | | Fix clang compiler warningClaire Wolf2020-05-081-2/+2
* | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-085-9/+26
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| * | | Reorder cases to avoid fall-through warningXiretza2020-05-071-3/+3
| * | | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-075-6/+23
* | | | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-079-52/+163
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* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-079-19/+142
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| * | | Fix the other "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-021-7/+19
| * | | Add plusargs for output files in test_autotb outputClaire Wolf2020-05-021-3/+10
| * | | Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
| * | | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| * | | Add tests based on the test case from #1990Claire Wolf2020-05-021-0/+46
| * | | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-025-7/+22
| * | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs...Claire Wolf2020-05-026-7/+57
* | | | Merge pull request #2034 from YosysHQ/eddie/abc_remoteEddie Hung2020-05-071-1/+1
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| * | | Makefile: git fetch all commits from $(ABCURL) repoEddie Hung2020-05-061-1/+1
* | | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-063-1/+23
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| * | | verilog: allow null gen-if then blockZachary Snow2020-05-063-1/+23
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