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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-12 15:40:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-12 15:40:48 -0700 |
| commit | 27b7ffc75444583bbecc70e2d7e2e84bc321f2cf (patch) | |
| tree | 0526ccdfe164cb9c36450d391f47ea9c21f6e0c1 | |
| parent | 4ecae8a6735f71e0dd9e3cc8eb0e7855299a78bc (diff) | |
| download | yosys-27b7ffc75444583bbecc70e2d7e2e84bc321f2cf.tar.gz yosys-27b7ffc75444583bbecc70e2d7e2e84bc321f2cf.tar.bz2 yosys-27b7ffc75444583bbecc70e2d7e2e84bc321f2cf.zip | |
ice40: fix ICESTORM_LC process sensitivity
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 6a0e3031e..5d107989d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1908,7 +1908,7 @@ module ICESTORM_LC ( o_reg <= SR_pd ? SET_NORESET : lut_o; reg o_reg_async = 1'b0; - always @(posedge polarized_clk, posedge SR) + always @(posedge polarized_clk, posedge SR_pd) if (SR_pd) o_reg_async <= SET_NORESET; else if (CEN_pu) |