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authorClaire Wolf <claire@symbioticeda.com>2020-05-01 17:25:33 +0200
committerClaire Wolf <claire@symbioticeda.com>2020-05-02 11:21:01 +0200
commit88185f8959dc53fd60605747cc93a6129fc1bab3 (patch)
tree005574671eb4573a9089dda8e22584be03e236d5
parent749c2ff84a618cdb1d0c38fefde9445ece42e6fb (diff)
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Fix handling of signed indices in bit slices
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
-rw-r--r--frontends/ast/genrtlil.cc11
1 files changed, 8 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 37cbb8a83..85d8e106b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1212,13 +1212,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone());
fake_ast->children[0]->delete_children();
- RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
+
+ int fake_ast_width = 0;
+ bool fake_ast_sign = true;
+ fake_ast->children[1]->detectSignWidth(fake_ast_width, fake_ast_sign);
+ RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign);
+
if (id2ast->range_right != 0) {
- shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
+ shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast_sign);
fake_ast->children[1]->is_signed = true;
}
if (id2ast->range_swapped) {
- shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
+ shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
fake_ast->children[1]->is_signed = true;
}
if (GetSize(shift_val) >= 32)