Merge pull request #2045 from YosysHQ/eddie/fix2042

verilog: error if no direction given for task arguments, default to input in SV mode

6 files changed, 107 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index a481dd92b..cd6179879 100644
--- a/Makefile
+++ b/Makefile
@@ -780,6 +780,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh
+	+cd tests/verilog && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index db9a130cf..f250d7685 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -853,7 +853,19 @@ task_func_port:
 		}
 		if (astbuf2 && astbuf2->children.size() != 2)
 			frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
-	} wire_name | wire_name;
+	} wire_name |
+	{
+		if (!astbuf1) {
+			if (!sv_mode)
+				frontend_verilog_yyerror("task/function argument direction missing");
+			albuf = new dict<IdString, AstNode*>;
+			astbuf1 = new AstNode(AST_WIRE);
+			current_wire_rand = false;
+			current_wire_const = false;
+			astbuf1->is_input = true;
+			astbuf2 = NULL;
+		}
+	} wire_name;
 
 task_func_body:
 	task_func_body behavioral_stmt |
diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/verilog/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
new file mode 100644
index 000000000..e815d7fc5
--- /dev/null
+++ b/tests/verilog/bug2042-sv.ys
@@ -0,0 +1,59 @@
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b
+);
+
+    task SomeTaskName(a);
+       b = ~a;
+    endtask
+
+    always @*
+        SomeTaskName(a);
+
+    assert property (b == ~a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b, c
+);
+
+    task SomeTaskName(x, output y, z);
+       y = ~x;
+       z = x;
+    endtask
+
+    always @*
+        SomeTaskName(a, b, c);
+
+    assert property (b == ~a);
+    assert property (c == a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
new file mode 100644
index 000000000..f9d8e2837
--- /dev/null
+++ b/tests/verilog/bug2042.ys
@@ -0,0 +1,11 @@
+logger -expect error "task/function argument direction missing" 1
+read_verilog <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/verilog/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk