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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 12:18:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 12:18:02 -0700 |
| commit | 2e911bc806d0a54e4d7e84ef2218ff088ea20b5f (patch) | |
| tree | 1ddb294e76e2a20bf9fa95430439bf173ff73557 | |
| parent | 584780d776c92bc91731dbc2710dd8d9a624dc70 (diff) | |
| download | yosys-2e911bc806d0a54e4d7e84ef2218ff088ea20b5f.tar.gz yosys-2e911bc806d0a54e4d7e84ef2218ff088ea20b5f.tar.bz2 yosys-2e911bc806d0a54e4d7e84ef2218ff088ea20b5f.zip | |
test: add failing test
| -rw-r--r-- | tests/verilog/upto.ys | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys new file mode 100644 index 000000000..d87f4424e --- /dev/null +++ b/tests/verilog/upto.ys @@ -0,0 +1,5 @@ +read_verilog <<EOT +module top(input [-128:-65] a); +endmodule +EOT +dump |