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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:59:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:59:38 -0700 |
| commit | 5be4b00a0dad4c6fe281a0e925daeae26715f215 (patch) | |
| tree | 1a2491d7c1885ad384c22176c5b4e6617f9095c3 | |
| parent | aa4a69f89be9fcdcf20ca1c28d67444b994ec479 (diff) | |
| download | yosys-5be4b00a0dad4c6fe281a0e925daeae26715f215.tar.gz yosys-5be4b00a0dad4c6fe281a0e925daeae26715f215.tar.bz2 yosys-5be4b00a0dad4c6fe281a0e925daeae26715f215.zip | |
opt_clean: improve warning message
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 | ||||
| -rw-r--r-- | tests/opt/opt_clean_init.ys | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 72ecc30e7..f7de02164 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -473,7 +473,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose) goto next_wire; if (mapped_wire_bit != init[i]) { - log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit)); + log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i])); goto next_wire; } } diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys index bfc383955..0d567608d 100644 --- a/tests/opt/opt_clean_init.ys +++ b/tests/opt/opt_clean_init.ys @@ -1,4 +1,4 @@ -logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1 +logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1 logger -expect-no-warnings read_verilog <<EOT module top; |