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* | opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-073-28/+145
* | Bump versiongithub-actions[bot]2022-05-071-1/+1
* | include latest abc changesMiodrag Milanovic2022-05-061-1/+1
* | include latest abc changesMiodrag Milanovic2022-05-061-1/+1
* | Merge pull request #3300 from imhcyx/masterMiodrag Milanović2022-05-061-1/+1
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| * | memory_share: fix wrong argidx in extra_argsimhcyx2022-05-051-1/+1
* | | Include abc change to fix FreeBSD buildMiodrag Milanovic2022-05-061-1/+1
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* | Bump versiongithub-actions[bot]2022-05-051-1/+1
* | abc: Use dict/pool instead of std::map/std::setMarcelina Kościelnicka2022-05-041-14/+14
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* Bump versiongithub-actions[bot]2022-05-031-1/+1
* AIM file could have gaps in or between inputs and initsMiodrag Milanovic2022-05-021-3/+6
* Bump versiongithub-actions[bot]2022-04-301-1/+1
* Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ffMiodrag Milanović2022-04-291-0/+1
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| * Ignore merging past ffs that we are not properly mergingMiodrag Milanovic2022-04-291-0/+1
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* Bump versiongithub-actions[bot]2022-04-261-1/+1
* Add missing parameters for ecp5Rick Luiken2022-04-252-1/+2
* Merge pull request #3287 from jix/smt2-conditional-storeJannis Harder2022-04-251-2/+4
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| * smt2: Make write port array stores conditional on nonzero write maskJannis Harder2022-04-201-2/+4
* | Merge pull request #3257 from jix/tribuf-formalJannis Harder2022-04-251-3/+46
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| * | tribuf: `-formal` option: convert all to logic and detect conflictsJannis Harder2022-04-121-3/+46
* | | Merge pull request #3290 from mpasternacki/bugfix/freebsd-buildMiodrag Milanović2022-04-251-0/+3
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| * | | Fix build on FreeBSD, which has no alloca.hMaciej Pasternacki2022-04-241-0/+3
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* | | Merge pull request #3289 from YosysHQ/micko/sim_improveMiodrag Milanović2022-04-252-29/+74
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| * | Match $anyseq input if connected to public wireMiodrag Milanovic2022-04-221-6/+12
| * | Treat $anyseq as input from FSTMiodrag Milanovic2022-04-221-0/+21
| * | Ignore change on last edgeMiodrag Milanovic2022-04-221-4/+5
| * | Last sample from input does not represent changeMiodrag Milanovic2022-04-221-1/+2
| * | latches are always set to zeroMiodrag Milanovic2022-04-221-6/+1
| * | If not multiclock, output only on clock edgesMiodrag Milanovic2022-04-221-0/+18
| * | Set init state for all wires from FST and set pastMiodrag Milanovic2022-04-221-13/+12
| * | Fix multiclock for btor2 witnessMiodrag Milanovic2022-04-221-5/+9
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* | Bump versiongithub-actions[bot]2022-04-191-1/+1
* | Merge pull request #3280 from YosysHQ/micko/fix_readaiwMiodrag Milanović2022-04-182-3/+3
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| * | Update abcMiodrag Milanovic2022-04-181-1/+1
| * | Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
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* | verific: allow memories to be inferred in loops (vhdl)Miodrag Milanovic2022-04-181-0/+1
* | Merge pull request #3282 from nakengelhardt/verific_loop_ramsMiodrag Milanović2022-04-181-0/+1
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| * | verific: allow memories to be inferred in loopsN. Engelhardt2022-04-151-0/+1
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* | Bump versiongithub-actions[bot]2022-04-161-1/+1
* | memory_share: Fix up mismatched address widths.Marcelina Kościelnicka2022-04-151-0/+14
* | opt_dff: Fix behavior on $ff with D == Q.Marcelina Kościelnicka2022-04-151-1/+1
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* Bump versiongithub-actions[bot]2022-04-091-1/+1
* Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fixMiodrag Milanović2022-04-081-9/+11
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| * Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
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* Merge pull request #3273 from modwizcode/fix-buildMiodrag Milanović2022-04-082-1/+12
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| * Makefile: properly conditionalize features requiring compression.Iris Johnson2022-04-072-1/+12
* | pass jny: flipped the defaults for the inclusion of various bits of metadataAki Van Ness2022-04-081-30/+30
* | pass jny: ensured the cell collection is cleared between modulesAki Van Ness2022-04-081-0/+1
* | pass jny: fixed missing quotes around the type value for the cell sortAki Van Ness2022-04-081-1/+1
* | pass jny: fixed the backslash escape for stringsAki Van Ness2022-04-081-2/+1
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