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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 12:03:39 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 12:03:39 +0200 |
commit | c989adcc2d466bb3e2e83cf67ad0a193f6628fa6 (patch) | |
tree | f3d830e5481ae9e578f2915bc1bdd9dc518595f4 | |
parent | 75032a565d22506ae7910bfa00e2b71558a30e26 (diff) | |
download | yosys-c989adcc2d466bb3e2e83cf67ad0a193f6628fa6.tar.gz yosys-c989adcc2d466bb3e2e83cf67ad0a193f6628fa6.tar.bz2 yosys-c989adcc2d466bb3e2e83cf67ad0a193f6628fa6.zip |
If not multiclock, output only on clock edges
-rw-r--r-- | passes/sat/sim.cc | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 967f7f227..73e03067b 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1782,6 +1782,12 @@ struct AIWWriter : public OutputWriter log_error("Index %d for wire %s is out of range\n", index, log_signal(w)); if (type == "input") { aiw_inputs[variable] = SigBit(w,index-w->start_offset); + if (worker->clock.count(escaped_s)) { + clocks[variable] = true; + } + if (worker->clockn.count(escaped_s)) { + clocks[variable] = false; + } } else if (type == "init") { aiw_inits[variable] = SigBit(w,index-w->start_offset); } else if (type == "latch") { @@ -1823,6 +1829,17 @@ struct AIWWriter : public OutputWriter first = false; } + bool skip = false; + for (auto it : clocks) + { + auto val = it.second ? State::S1 : State::S0; + SigBit bit = aiw_inputs.at(it.first); + auto v = current[mapping[bit.wire]].bits.at(bit.offset); + if (v == val) + skip = true; + } + if (skip) + continue; for (int i = 0;; i++) { if (aiw_inputs.count(i)) { @@ -1852,6 +1869,7 @@ struct AIWWriter : public OutputWriter std::ofstream aiwfile; dict<int, std::pair<SigBit, bool>> aiw_latches; dict<int, SigBit> aiw_inputs, aiw_inits; + dict<int, bool> clocks; std::map<Wire*,int> mapping; }; |