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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-05-06 09:17:59 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-06 09:17:59 +0200 |
| commit | 384d2120ee336c7f709423e69794802652985d74 (patch) | |
| tree | ffd18cb3308bd63864139d7efdf5d3283619311d | |
| parent | 52d8ddee0ccde0afccbc703d673e46457f63672b (diff) | |
| parent | 71166eeecf5d3c9fcdd86e692511e772f3e437a1 (diff) | |
| download | yosys-384d2120ee336c7f709423e69794802652985d74.tar.gz yosys-384d2120ee336c7f709423e69794802652985d74.tar.bz2 yosys-384d2120ee336c7f709423e69794802652985d74.zip | |
Merge pull request #3300 from imhcyx/master
memory_share: fix wrong argidx in extra_args
| -rw-r--r-- | passes/memory/memory_share.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 1ddc13f90..5cb11d62b 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -555,7 +555,7 @@ struct MemorySharePass : public Pass { } break; } - extra_args(args, 1, design); + extra_args(args, argidx, design); MemoryShareWorker msw(design, flag_widen, flag_sat); for (auto module : design->selected_modules()) |