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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 13:46:11 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 13:46:11 +0200 |
| commit | 33f4009bb559eefaabd19b3dde06639889eb1eed (patch) | |
| tree | e2431ab670ecd53e5e52a5733758ee73f70942d6 | |
| parent | 83cad82b295255d59e2162d599bbd4485b688c6a (diff) | |
| download | yosys-33f4009bb559eefaabd19b3dde06639889eb1eed.tar.gz yosys-33f4009bb559eefaabd19b3dde06639889eb1eed.tar.bz2 yosys-33f4009bb559eefaabd19b3dde06639889eb1eed.zip | |
Last sample from input does not represent change
| -rw-r--r-- | passes/sat/sim.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index f480168bd..345ca3494 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1805,8 +1805,9 @@ struct AIWWriter : public OutputWriter std::map<int, Yosys::RTLIL::Const> current; bool first = true; - for(auto& d : worker->output_data) + for (auto iter = worker->output_data.begin(); iter != std::prev(worker->output_data.end()); ++iter) { + auto& d = *iter; for (auto &data : d.second) { current[data.first] = data.second; |