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| author | Rick Luiken <rick-luiken@live.nl> | 2022-04-08 14:41:48 +0200 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2022-04-25 15:31:41 +0100 |
| commit | 414dc25a96a724af2f13d680d1aee1da0d10e0a2 (patch) | |
| tree | a9360fa5703d31a9228f664e2eacea045fcdf3f3 | |
| parent | 6ae0b51c76cd9a79c10d6516ef14c54339551ff4 (diff) | |
| download | yosys-414dc25a96a724af2f13d680d1aee1da0d10e0a2.tar.gz yosys-414dc25a96a724af2f13d680d1aee1da0d10e0a2.tar.bz2 yosys-414dc25a96a724af2f13d680d1aee1da0d10e0a2.zip | |
Add missing parameters for ecp5
| -rw-r--r-- | techlibs/ecp5/cells_bb.v | 2 | ||||
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index e616d24d6..fc352a52c 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -223,7 +223,7 @@ endmodule (* blackbox *) module IDDRX2F( - input D, SCLK, ECLK, RST, + input D, SCLK, ECLK, RST, ALIGNWD, output Q0, Q1, Q2, Q3 ); parameter GSR = "ENABLED"; diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 76099f493..f9d503deb 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -799,6 +799,7 @@ module DP16KD( parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; endmodule `ifndef NO_INCLUDES |