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* Revert "Add test that is expecting to fail"Eddie Hung2019-10-081-20/+0
* Revert "Be mindful that sigmap(wire) could have dupes when checking \init"Eddie Hung2019-10-081-4/+1
* Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-084-50/+145
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| * Use `sat -tempinduct` and comments for why equiv_opt not sufficientEddie Hung2019-10-031-1/+8
| * Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-022-25/+28
| * Fix testEddie Hung2019-10-021-2/+12
| * Merge branch 'eddie/fix_sat_init' into eddie/fix1427Eddie Hung2019-10-022-1/+24
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| | * Be mindful that sigmap(wire) could have dupes when checking \initEddie Hung2019-10-021-1/+4
| | * Add test that is expecting to failEddie Hung2019-10-021-0/+20
| * | Update testEddie Hung2019-10-021-13/+3
| * | Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
| * | Add testEddie Hung2019-10-021-0/+31
* | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-083-13/+19
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| * | | Add -async2sync to help text as per @daveshah1Eddie Hung2019-10-041-1/+4
| * | | Restore part of docEddie Hung2019-10-031-1/+2
| * | | Disable equiv check for ice40 latchesEddie Hung2019-10-031-6/+3
| * | | Add new -async2sync optionEddie Hung2019-10-031-1/+11
| * | | Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
| * | | Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"Eddie Hung2019-10-031-2/+0
| * | | Revert "Update doc for equiv_opt"Eddie Hung2019-10-031-3/+2
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* | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0834-309/+316
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| * \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-048-185/+33
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| * | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0434-305/+313
* | | | | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-085-72/+364
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| * | | | | Missed thisEddie Hung2019-10-051-3/+4
| * | | | | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
| * | | | | Add note on pattern detectorEddie Hung2019-10-051-3/+7
| * | | | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| * | | | | Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
| * | | | | Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
| * | | | | Fix commentEddie Hung2019-10-041-1/+1
| * | | | | Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
| * | | | | Retry on fixing TODOsEddie Hung2019-10-042-13/+1
| * | | | | Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| * | | | | More comments, cleanupEddie Hung2019-10-042-41/+108
| * | | | | Fix TODOsEddie Hung2019-10-042-20/+0
| * | | | | ConsistencyEddie Hung2019-10-041-3/+3
| * | | | | Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
* | | | | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-062-0/+26
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| * | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-052-0/+26
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* | | | | | Update README.mdClifford Wolf2019-10-051-1/+1
* | | | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-052-2/+7
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| * | | | | Fixes for MSVC buildMiodrag Milanovic2019-10-042-2/+7
* | | | | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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* | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-042-5/+19
* | | | | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
* | | | | Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
* | | | | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
* | | | | Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
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* | | | Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4