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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:45:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:45:53 -0700 |
| commit | bd5889640bbcbb11c80360893fcf17d9399cef8a (patch) | |
| tree | 33241b9c78fc4dec49e0a2e3607dfcf9e7759819 | |
| parent | 7a6dec1cef9c6a44dafe83d884abaf06dc77ab07 (diff) | |
| download | yosys-bd5889640bbcbb11c80360893fcf17d9399cef8a.tar.gz yosys-bd5889640bbcbb11c80360893fcf17d9399cef8a.tar.bz2 yosys-bd5889640bbcbb11c80360893fcf17d9399cef8a.zip | |
Disable equiv check for ice40 latches
| -rw-r--r-- | tests/ice40/latches.ys | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index f3562559e..708734e44 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,14 +1,11 @@ read_verilog latches.v -design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +# Can't run any sort of equivalence check because latches are blown to LUTs +#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load read +#design -load preopt synth_ice40 cd top select -assert-count 4 t:SB_LUT4 |