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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:51:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:51:53 -0700 |
| commit | a9efd2e81cd502665ee034f64c85b11e34dfd9bb (patch) | |
| tree | 337b1f7eb960d4b621b0979f00eea5e131fabaa7 | |
| parent | bd5889640bbcbb11c80360893fcf17d9399cef8a (diff) | |
| download | yosys-a9efd2e81cd502665ee034f64c85b11e34dfd9bb.tar.gz yosys-a9efd2e81cd502665ee034f64c85b11e34dfd9bb.tar.bz2 yosys-a9efd2e81cd502665ee034f64c85b11e34dfd9bb.zip | |
Restore part of doc
| -rw-r--r-- | passes/equiv/equiv_opt.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index d13e46ce4..ec1200488 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -32,7 +32,8 @@ struct EquivOptPass:public ScriptPass log("\n"); log(" equiv_opt [options] [command]\n"); log("\n"); - log("This command checks circuit equivalence before and after an optimization pass.\n"); + log("This command uses temporal induction to check circuit equivalence before and\n"); + log("after an optimization pass.\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); |