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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 11:11:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 11:11:50 -0700 |
| commit | 045f34403889b69f3ac3ac08d96e5cf1fae787d1 (patch) | |
| tree | 64efd40a13665b66c34182c4b5dec1b3c30ba471 | |
| parent | e9645c7fa7fc349afad103ff8736699bb4dc0412 (diff) | |
| download | yosys-045f34403889b69f3ac3ac08d96e5cf1fae787d1.tar.gz yosys-045f34403889b69f3ac3ac08d96e5cf1fae787d1.tar.bz2 yosys-045f34403889b69f3ac3ac08d96e5cf1fae787d1.zip | |
Use `sat -tempinduct` and comments for why equiv_opt not sufficient
| -rw-r--r-- | tests/various/peepopt.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 4b130578b..ee5ad8a1a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,6 +188,13 @@ endmodule EOT proc +# NB: equiv_opt uses equiv_induct which covers +# only the induction half of temporal induction +# --- missing the base-case half +# This makes it akin to `sat -tempinduct-inductonly` +# instead of `sat -tempinduct-baseonly` or +# `sat -tempinduct` which is necessary for this +# testcase #equiv_opt -assert peepopt design -save gold @@ -197,7 +204,7 @@ design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -seq 1 -verify -prove-asserts -show-ports miter +sat -tempinduct -verify -prove-asserts -show-ports miter design -load gate select -assert-count 1 t:$dff r:WIDTH=4 %i |