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authorEddie Hung <eddie@fpgeh.com>2019-10-04 13:38:09 -0700
committerEddie Hung <eddie@fpgeh.com>2019-10-04 22:31:04 -0700
commit77d7a5c14a6cf7c16b69338ed91d1b9166dba065 (patch)
tree927cb52fc479b39ddc395b39f02df28e0b263cbe
parent52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67 (diff)
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Retry on fixing TODOs
-rw-r--r--passes/pmgen/xilinx_dsp.pmg9
-rw-r--r--passes/pmgen/xilinx_dsp_CREG.pmg5
2 files changed, 1 insertions, 13 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 8a2c2caf5..dbc3f7455 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -100,14 +100,10 @@ code sigA sigB sigC sigD sigM clock
sigM.append(P[i]);
}
log_assert(nusers(P.extract_end(i)) <= 1);
+ log_assert(!sigM.empty());
}
else
sigM = P;
- // TODO: Check if necessary
- // This sigM could have no users if downstream $add
- // is narrower than $mul result, for example
- if (sigM.empty())
- reject;
clock = port(dsp, \CLK, SigBit());
endcode
@@ -160,12 +156,9 @@ match preAdd
endmatch
code sigA sigD
- // TODO: Check if this is necessary?
if (preAdd) {
sigA = port(preAdd, \A);
sigD = port(preAdd, \B);
- if (GetSize(sigA) < GetSize(sigD))
- std::swap(sigA, sigD);
}
endcode
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index b87a686a1..3d911b478 100644
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -79,11 +79,6 @@ endcode
// (attached to at most two $mux cells that implement clock-enable or
// reset functionality, using the in_dffe subpattern)
code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
- // TODO: Any downside to allowing this?
- // If this DSP implements an accumulator, do not attempt to match
- if (sigC == sigP)
- reject;
-
argQ = sigC;
subpattern(in_dffe);
if (dff) {