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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 08:56:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 08:56:37 -0700 |
| commit | 991c2ca95bfac2bedd9fd622dbef15611021a8be (patch) | |
| tree | d97236975007054d0c294c79420207efacf94a72 | |
| parent | ebb059896a55efacf1d90f78dbd25faff30969e2 (diff) | |
| download | yosys-991c2ca95bfac2bedd9fd622dbef15611021a8be.tar.gz yosys-991c2ca95bfac2bedd9fd622dbef15611021a8be.tar.bz2 yosys-991c2ca95bfac2bedd9fd622dbef15611021a8be.zip | |
Add comment on why we have to match for clock-enable/reset muxes
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 5 | ||||
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 4 | ||||
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 5 |
3 files changed, 11 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 09d94ff4b..604aa222b 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -441,7 +441,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 3f8486406..2408d483a 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -105,7 +105,9 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. +// 'Q' input. Typically, this task would be handled by other Yosys passes +// such as dff2dffe, but since DSP inference happens much before this, these +// patterns have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 42d1aee6c..7a32df2b7 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -298,7 +298,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument |