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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 16:08:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 16:08:46 -0700 |
| commit | f46ac1df9f8847dac9d9851f2f948d93a1064ff1 (patch) | |
| tree | 9d0305c30617384730df1941889e5ce6cfaff85c | |
| parent | c28d4b804720c2cf0086e921748219150e9631b5 (diff) | |
| download | yosys-f46ac1df9f8847dac9d9851f2f948d93a1064ff1.tar.gz yosys-f46ac1df9f8847dac9d9851f2f948d93a1064ff1.tar.bz2 yosys-f46ac1df9f8847dac9d9851f2f948d93a1064ff1.zip | |
Be mindful that sigmap(wire) could have dupes when checking \init
| -rw-r--r-- | passes/sat/sat.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430bba1e8..93a4f225e 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -265,15 +265,18 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.size() == rhs.size()); + dict<RTLIL::SigBit,SigBit> seen_init; RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; } + else + seen_init[bit] = rhs[i]; } if (removed_bits.size()) |