| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | | | | | | | abc9 needs a clean afterwards | Eddie Hung | 2019-12-16 | 1 | -2/+4 | |
| | | * | | | | | | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop | Eddie Hung | 2019-12-16 | 1 | -5/+27 | |
| | | * | | | | | | | | | Use sigmap signal | Eddie Hung | 2019-12-16 | 1 | -1/+1 | |
| | | * | | | | | | | | | Skip $inout transformation if not a PI | Eddie Hung | 2019-12-16 | 1 | -3/+5 | |
| | | * | | | | | | | | | Revert "write_xaiger: use sigmap bits more consistently" | Eddie Hung | 2019-12-16 | 1 | -4/+5 | |
| | | * | | | | | | | | | write_xaiger: use sigmap bits more consistently | Eddie Hung | 2019-12-16 | 1 | -5/+4 | |
| | | * | | | | | | | | | Name inputs/outputs of aiger 'i%d' and 'o%d' | Eddie Hung | 2019-12-13 | 1 | -13/+6 | |
| | | * | | | | | | | | | Remove 'clkpart' entry in CHANGELOG | Eddie Hung | 2019-12-12 | 1 | -1/+0 | |
| | | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 18 | -64/+238 | |
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| | | * | | | | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
| | | * | | | | | | | | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 | |
| | | * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 19 | -971/+1773 | |
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| | | * | | | | | | | | | | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 2 | -94/+87 | |
| | | * | | | | | | | | | | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 | |
| | | * | | | | | | | | | | | Do not connect undriven POs to 1'bx | Eddie Hung | 2019-12-06 | 1 | -8/+3 | |
| | | * | | | | | | | | | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type as | Eddie Hung | 2019-12-06 | 1 | -39/+15 | |
| | | * | | | | | | | | | | | Fix writing non-whole modules, including inouts and keeps | Eddie Hung | 2019-12-06 | 1 | -90/+81 | |
| | | * | | | | | | | | | | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 | |
| | | * | | | | | | | | | | | write_xaiger to support part-selected modules again | Eddie Hung | 2019-12-05 | 1 | -11/+37 | |
| | | * | | | | | | | | | | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 | |
| | | * | | | | | | | | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 3 | -313/+0 | |
| | | * | | | | | | | | | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 | |
| | | * | | | | | | | | | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 | |
| | | * | | | | | | | | | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 2 | -118/+292 | |
| | | * | | | | | | | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 | |
| | | * | | | | | | | | | | | Bump ABC to get "&verify -s" fix | Eddie Hung | 2019-12-04 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 | |
| | | * | | | | | | | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 | |
| | | * | | | | | | | | | | | Cleanup | Eddie Hung | 2019-12-03 | 1 | -11/+12 | |
| | | * | | | | | | | | | | | Add assertion | Eddie Hung | 2019-12-03 | 1 | -0/+1 | |
| | | * | | | | | | | | | | | write_xaiger to consume abc9_init attribute for abc9_flops | Eddie Hung | 2019-12-03 | 1 | -34/+28 | |
| | | * | | | | | | | | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 2 | -4/+24 | |
| | | * | | | | | | | | | | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 | |
| | | * | | | | | | | | | | | Update ABCREV for upstream bugfix | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 | |
| | | * | | | | | | | | | | | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 | |
| | | * | | | | | | | | | | | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 | |
| | | * | | | | | | | | | | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-01 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | Use pool<> not std::set<> for determinism | Eddie Hung | 2019-12-01 | 1 | -4/+4 | |
| | | * | | | | | | | | | | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 | |
| | | * | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-28 | 1 | -1/+1 | |
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| | | | * | | | | | | | | | | | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
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| | | | * | | | | | | | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 | |
| | | | * | | | | | | | | | | | Add multiple driver testcase | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
| | | * | | | | | | | | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 | |
| | | * | | | | | | | | | | | | Add comment, use sigmap | Eddie Hung | 2019-11-27 | 1 | -2/+2 | |
| | | * | | | | | | | | | | | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| | | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 5 | -7/+100 | |
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| | | * | | | | | | | | | | | | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 | |
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index : iCE40/yosys | |
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