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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 12:35:25 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 12:35:25 -0800 |
| commit | 403214f44d8f447ce4e367e2d7e135bfaabcb88d (patch) | |
| tree | a1febc78a0e0f41152b5fd5ffa69557ea56eb6c0 | |
| parent | 4bac6b13bef7e5a97271726c6cf445c02a818903 (diff) | |
| download | yosys-403214f44d8f447ce4e367e2d7e135bfaabcb88d.tar.gz yosys-403214f44d8f447ce4e367e2d7e135bfaabcb88d.tar.bz2 yosys-403214f44d8f447ce4e367e2d7e135bfaabcb88d.zip | |
Revert "Fold loop"
This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index f17a4c775..8b809b2e2 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -184,7 +184,6 @@ struct XAigerWriter if (bit != wirebit) alias_map[bit] = wirebit; input_bits.insert(wirebit); - undriven_bits.erase(bit); } if (wire->port_output || keep) { @@ -192,8 +191,6 @@ struct XAigerWriter if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); - if (!wire->port_input) - unused_bits.erase(bit); } else log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); @@ -201,6 +198,12 @@ struct XAigerWriter } } + for (auto bit : input_bits) + undriven_bits.erase(sigmap(bit)); + for (auto bit : output_bits) + if (!bit.wire->port_input) + unused_bits.erase(bit); + // TODO: Speed up toposort -- ultimately we care about // box ordering, but not individual AIG cells dict<SigBit, pool<IdString>> bit_drivers, bit_users; |