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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 10:21:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 10:21:57 -0800 |
| commit | 6c340112fee1bb8989cbd41923aaa627d77d5110 (patch) | |
| tree | e54a3aea57dae79efb15b6d3b36e4ef56b547e90 | |
| parent | c0339bbbf16cee8121417f69305c7601122ff70c (diff) | |
| download | yosys-6c340112fee1bb8989cbd41923aaa627d77d5110.tar.gz yosys-6c340112fee1bb8989cbd41923aaa627d77d5110.tar.bz2 yosys-6c340112fee1bb8989cbd41923aaa627d77d5110.zip | |
write_xaiger: use sigmap bits more consistently
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c080cca4d..cff3183c1 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -294,7 +294,7 @@ struct XAigerWriter output_bits.insert(b); if (!cell_known) - inout_bits.insert(b); + inout_bits.insert(I); } } } @@ -315,7 +315,7 @@ struct XAigerWriter SigBit O = sigmap(b); if (O != b) alias_map[O] = b; - input_bits.insert(b); + input_bits.insert(O); if (arrival) arrival_times[b] = arrival; @@ -542,9 +542,8 @@ struct XAigerWriter undriven_bits.erase(bit); } - // For inout ports, or keep-ed wires, then create a new wire with an - // $inout.out suffix, make it a PO driven by the existing inout, and - // inherit existing inout's drivers + // For inout ports, or keep-ed wires, which end up being both a PI and a + // a PO then replace the PO with a new wire with the $inout.out suffix for (auto bit : inout_bits) { RTLIL::Wire *wire = bit.wire; RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); |