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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 16:21:06 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 16:21:06 -0800 |
| commit | 69d8c1386a239372a2ab8910bf12d5d70701b7fa (patch) | |
| tree | e84514378ed3cddb6334a999039b2cc0e681f3a1 | |
| parent | fce527f4f7764ae2e2d5f6a7e01da59075f79350 (diff) | |
| download | yosys-69d8c1386a239372a2ab8910bf12d5d70701b7fa.tar.gz yosys-69d8c1386a239372a2ab8910bf12d5d70701b7fa.tar.bz2 yosys-69d8c1386a239372a2ab8910bf12d5d70701b7fa.zip | |
Do not connect undriven POs to 1'bx
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 9374f1ab3..084107b35 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -1005,15 +1005,10 @@ void AigerReader::post_process() if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; - } - if (wire->port_input) { - if (other_wire) + if (wire->port_input) module->connect(other_wire, SigSpec(wire, i)); - } - else { - // Since we skip POs that are connected to Sx, - // re-connect them here - module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx)); + else + module->connect(SigSpec(wire, i), other_wire); } } } |