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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-03 19:21:42 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-03 19:21:42 -0800 |
| commit | d66d06b91df4aade84107b59b2b1f32188a3995e (patch) | |
| tree | 9ec9aac341934249ae6c3ecc7780da5b428df494 | |
| parent | df52bc80d80e384dddf50a01fa970d1aa36123f2 (diff) | |
| download | yosys-d66d06b91df4aade84107b59b2b1f32188a3995e.tar.gz yosys-d66d06b91df4aade84107b59b2b1f32188a3995e.tar.bz2 yosys-d66d06b91df4aade84107b59b2b1f32188a3995e.zip | |
Add assertion
| -rw-r--r-- | passes/techmap/abc9.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 5139cb80b..5b4100574 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1107,6 +1107,7 @@ struct Abc9Pass : public Pass { Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str())); if (abc9_clock_wire == NULL) log_error("'%s.$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module)); + log_assert(GetSize(abc9_clock_wire) == 1); SigBit abc9_clock = sigmap(abc9_clock_wire); auto r = clocks.insert(abc9_clock.wire); if (r.second) { |