| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | netlists-disp_vhdl: handle unconnected outputs. Fix #1050 | Tristan Gingold | 2019-12-04 | 1 | -10/+10 |
| * | netlists-disp_vhdl: force conversion for mux2 | Tristan Gingold | 2019-11-28 | 1 | -1/+2 |
| * | netlists: remove port API (make it easier to interface). | Tristan Gingold | 2019-11-28 | 1 | -18/+27 |
| * | netlists: remove port_inout. | Tristan Gingold | 2019-11-28 | 1 | -2/+0 |
| * | netlists-disp_vhdl: handle UB32 in Disp_Const_Bit. Fix #1039 | Tristan Gingold | 2019-11-27 | 1 | -0/+8 |
| * | introduce package utils_io. | Tristan Gingold | 2019-11-21 | 1 | -20/+1 |
| * | netlists: initial support of net of width 0. | Tristan Gingold | 2019-11-12 | 1 | -1/+0 |
| * | netlists: expand dyn_insert_en | Tristan Gingold | 2019-11-11 | 1 | -0/+1 |
| * | netlists: add more support for dyn_insert_en | Tristan Gingold | 2019-11-11 | 1 | -6/+17 |
| * | netlists-disp_vhdl: handle truncate to width 1. | Tristan Gingold | 2019-11-05 | 1 | -2/+7 |
| * | netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant. | Tristan Gingold | 2019-10-28 | 1 | -1/+3 |
| * | synth: generate cover for assertion precedent. | Tristan Gingold | 2019-10-21 | 1 | -0/+4 |
| * | netlists-disp_vhdl: display memory initialization value. | Tristan Gingold | 2019-10-20 | 1 | -2/+46 |
| * | netlists-disp_vhdl: display memories. | Tristan Gingold | 2019-10-17 | 1 | -1/+97 |
| * | netlists-disp_vhdl: fix pasto on id_asr. | Tristan Gingold | 2019-10-10 | 1 | -5/+5 |
| * | netlists-disp_vhdl: handle const_SB32 | Tristan Gingold | 2019-10-09 | 1 | -1/+2 |
| * | netlists: remove get_parent renaming for input. | Tristan Gingold | 2019-10-06 | 1 | -2/+2 |
| * | netlists: remove renaming of Get_Parent for Net. | Tristan Gingold | 2019-10-06 | 1 | -4/+5 |
| * | netlists: remove get_name renaming for modules. | Tristan Gingold | 2019-10-06 | 1 | -4/+4 |
| * | netlists: Remove Get_Name renaming for instances. | Tristan Gingold | 2019-10-06 | 1 | -2/+2 |
| * | netlists-disp_vhdl: handle lsl, rol, asr, nand, nor. | Tristan Gingold | 2019-10-04 | 1 | -0/+18 |
| * | netlists-disp_vhdl: add qualification when needed for = | Tristan Gingold | 2019-10-04 | 1 | -5/+24 |
| * | netlists-disp_vhdl: handle empty operand for concat2, add | Tristan Gingold | 2019-10-04 | 1 | -1/+30 |
| * | netlists-disp_vhdl: handle id_neg | Tristan Gingold | 2019-10-04 | 1 | -0/+2 |
| * | netlists: rename id_memidx1 to id_memidx | Tristan Gingold | 2019-10-03 | 1 | -1/+1 |
| * | synth: replace memidx2 by addidx; handle some 2d arrays. | Tristan Gingold | 2019-10-03 | 1 | -3/+28 |
| * | synth: simplify dyn_insert. | Tristan Gingold | 2019-10-02 | 1 | -3/+3 |
| * | synth: simplify id_dyn_extract. | Tristan Gingold | 2019-10-02 | 1 | -8/+1 |
| * | synth: introduce memidx1 | Tristan Gingold | 2019-10-02 | 1 | -0/+15 |
| * | netlists-disp_vhdl: handle Const_Log, add comments, fix assertion. | Tristan Gingold | 2019-10-02 | 1 | -1/+22 |
| * | netlists-disp_vhdl: display constant signals connected to user submodules. | Tristan Gingold | 2019-10-01 | 1 | -0/+2 |
| * | synth: add support for integer rem. | Tristan Gingold | 2019-10-01 | 1 | -0/+6 |
| * | netlists-disp_vhdl: improve disp_x_lit. | Tristan Gingold | 2019-09-28 | 1 | -3/+9 |
| * | netlists-disp_vhdl: handle id_edge. | Tristan Gingold | 2019-09-28 | 1 | -0/+3 |
| * | synth: fix handling of single-bit memories. | Tristan Gingold | 2019-09-26 | 1 | -4/+11 |
| * | netlists-disp_vhdl: handle lsr. | Tristan Gingold | 2019-09-21 | 1 | -0/+4 |
| * | synth: use constant for constant values. | Tristan Gingold | 2019-09-21 | 1 | -30/+62 |
| * | synth: Add support for PSL cover directive (#930) | T. Meissner | 2019-09-19 | 1 | -0/+4 |
| * | synth: minor refactoring about const gates. | Tristan Gingold | 2019-09-15 | 1 | -36/+22 |
| * | synth: add const_x gate. | Tristan Gingold | 2019-09-11 | 1 | -1/+5 |
| * | synth: introduce slice type. | Tristan Gingold | 2019-09-11 | 1 | -0/+4 |
| * | synth: add const_sb32, add smul/umul. | Tristan Gingold | 2019-09-07 | 1 | -1/+1 |
| * | synth: handle const_bit in disp_constant_inline. | Tristan Gingold | 2019-09-04 | 1 | -0/+4 |
| * | synth: remove insert gate. | Tristan Gingold | 2019-08-31 | 1 | -22/+0 |
| * | netlists-disp_vhdl: do not used literals for prefixes. | Tristan Gingold | 2019-08-27 | 1 | -12/+53 |
| * | synth: set name to assert/assume gates. | Tristan Gingold | 2019-08-20 | 1 | -2/+8 |
| * | netlist: fix minor pasto. | Tristan Gingold | 2019-08-20 | 1 | -1/+1 |
| * | initial support for reduce and/or (#900) | Pepijn de Vos | 2019-08-20 | 1 | -0/+13 |
| * | synth: handle signed conversions in disp_vhdl. | Tristan Gingold | 2019-08-05 | 1 | -2/+6 |
| * | synth: handle signed integer comparisons (#878) | Pepijn de Vos | 2019-08-01 | 1 | -0/+12 |
