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simul
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*
simul: move assertions (not to trigger in case of errors)
Tristan Gingold
2022-09-11
1
-3
/
+3
|
*
simul: optimize resolution call only for std_logic
Tristan Gingold
2022-09-11
1
-5
/
+11
|
*
synth: fix and add checks for memory management.
Tristan Gingold
2022-09-10
1
-6
/
+17
|
*
simul: add support for protected objects
Tristan Gingold
2022-09-08
2
-2
/
+62
|
*
elab-vhdl_values: factorize code
Tristan Gingold
2022-09-07
1
-2
/
+2
|
*
simul: do not propagate errors from resolution function
Tristan Gingold
2022-09-07
1
-0
/
+3
|
*
simul: fix computation for number of drivers
Tristan Gingold
2022-09-06
1
-1
/
+2
|
*
synth: handle generics in blocks
Tristan Gingold
2022-09-06
2
-3
/
+21
|
*
simul: add an hook to display report/assert message
Tristan Gingold
2022-09-06
1
-14
/
+50
|
*
synth: use areapools
Tristan Gingold
2022-09-02
3
-90
/
+139
|
*
synth: factorize code for tracing statements execution
Tristan Gingold
2022-09-02
1
-3
/
+7
|
*
simul: detect multiple drivers for unresolved signals
Tristan Gingold
2022-09-02
1
-8
/
+93
|
*
simul-vhdl_simul: simplify procedure connect
Tristan Gingold
2022-08-26
1
-41
/
+22
|
*
simul: handle connections of records
Tristan Gingold
2022-08-25
1
-1
/
+18
|
*
synth: handle indexes/ranges in configurations for generate blocks
Tristan Gingold
2022-08-25
1
-1
/
+2
|
*
simul: improve support of float signals
Tristan Gingold
2022-08-24
1
-3
/
+7
|
*
simul: handle conversions and associations with constants
Tristan Gingold
2022-08-24
2
-70
/
+399
|
*
simul: simplify code
Tristan Gingold
2022-08-23
1
-16
/
+4
|
*
simul: factorize code to compute number of sources
Tristan Gingold
2022-08-23
4
-120
/
+50
|
*
simul-vhdl_debug: disp nbr sources
Tristan Gingold
2022-08-23
1
-1
/
+15
|
*
simul: add extra drivers for ports without sources
Tristan Gingold
2022-08-23
3
-14
/
+152
|
*
simul-vhdl_simul: handle waveforms in signal assignments
Tristan Gingold
2022-08-21
1
-40
/
+47
|
*
simul: rework assertions execution and error handling
Tristan Gingold
2022-08-21
1
-3
/
+4
|
*
simul: handle concurrent procedure calls (WIP)
Tristan Gingold
2022-08-21
1
-15
/
+95
|
*
simul: handle after clauses in signal assignment
Tristan Gingold
2022-08-21
1
-70
/
+93
|
*
simul-vhdl_simul: add support for PSL directives
Tristan Gingold
2022-08-20
2
-14
/
+267
|
*
simul-vhdl_debug: display connections
Tristan Gingold
2022-08-19
1
-5
/
+63
|
*
simul: handle resolved signals (WIP)
Tristan Gingold
2022-08-19
2
-43
/
+297
|
*
ghdlsimul: add an option to debug before elaboration
Tristan Gingold
2022-08-18
2
-3
/
+4
|
*
simul: handle individual associations
Tristan Gingold
2022-08-17
2
-4
/
+16
|
*
simul: add create_connects
Tristan Gingold
2022-08-17
4
-46
/
+144
|
*
simul: create terminals (WIP)
Tristan Gingold
2022-08-17
4
-8
/
+62
|
*
simul-vhdl_simul: add scalar terminal table
Tristan Gingold
2022-07-28
1
-0
/
+16
|
*
simul-vhdl_debug: add info terminal
Tristan Gingold
2022-07-28
1
-20
/
+69
|
*
simul: gather terminals
Tristan Gingold
2022-07-25
2
-0
/
+43
|
*
src/simul: rewrite of ghdl/simul based on synth
Tristan Gingold
2022-07-24
7
-0
/
+3759
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