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author | Tristan Gingold <tgingold@free.fr> | 2021-11-12 18:52:18 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-12 18:52:58 +0100 |
commit | 56735b0d1e92b4246ef53442236e89afe07aacdc (patch) | |
tree | 7b0c825edbc6021b269e89d187bc06fb93e997ad /testsuite/synth | |
parent | c2b6b4fe03c879753c76f5bee9f0ffe3b0e73f52 (diff) | |
download | ghdl-56735b0d1e92b4246ef53442236e89afe07aacdc.tar.gz ghdl-56735b0d1e92b4246ef53442236e89afe07aacdc.tar.bz2 ghdl-56735b0d1e92b4246ef53442236e89afe07aacdc.zip |
testsuite/synth: add a test for black boxes
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/blackbox01/blackbox1.vhdl | 20 | ||||
-rw-r--r-- | testsuite/synth/blackbox01/blackbox1_adder.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/blackbox01/tb_blackbox1.vhdl | 33 | ||||
-rwxr-xr-x | testsuite/synth/blackbox01/testsuite.sh | 14 |
4 files changed, 80 insertions, 0 deletions
diff --git a/testsuite/synth/blackbox01/blackbox1.vhdl b/testsuite/synth/blackbox01/blackbox1.vhdl new file mode 100644 index 000000000..01bef9ad8 --- /dev/null +++ b/testsuite/synth/blackbox01/blackbox1.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity blackbox1 is + port (a, b : in std_logic_vector(7 downto 0); + r : out std_logic_vector(7 downto 0)); +end blackbox1; + +architecture behav of blackbox1 is + component blackbox1_adder is + port (a, b : in std_logic_vector(7 downto 0); + r : out std_logic_vector(7 downto 0)); + end component; + signal t : std_logic_vector(7 downto 0); +begin + adder: blackbox1_adder + port map (a, b, t); + + r <= t and x"ee"; +end behav; diff --git a/testsuite/synth/blackbox01/blackbox1_adder.vhdl b/testsuite/synth/blackbox01/blackbox1_adder.vhdl new file mode 100644 index 000000000..579c5e70d --- /dev/null +++ b/testsuite/synth/blackbox01/blackbox1_adder.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity blackbox1_adder is + port (a, b : in std_logic_vector(7 downto 0); + r : out std_logic_vector(7 downto 0)); +end blackbox1_adder; + +architecture behav of blackbox1_adder is +begin + r <= std_logic_vector(unsigned(a) + unsigned(b)); +end behav; diff --git a/testsuite/synth/blackbox01/tb_blackbox1.vhdl b/testsuite/synth/blackbox01/tb_blackbox1.vhdl new file mode 100644 index 000000000..695be78d5 --- /dev/null +++ b/testsuite/synth/blackbox01/tb_blackbox1.vhdl @@ -0,0 +1,33 @@ +entity tb_blackbox1 is +end tb_blackbox1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_blackbox1 is + signal a, b : std_logic_vector(7 downto 0); + signal r :std_logic_vector(7 downto 0); +begin + dut: entity work.blackbox1 + port map (a, b, r); + + process + begin + a <= x"40"; + b <= x"04"; + wait for 1 ns; + assert r = x"44" severity failure; + + a <= x"b5"; + b <= x"11"; + wait for 1 ns; + assert r = x"c6" severity failure; + + a <= x"b5"; + b <= x"23"; + wait for 1 ns; + assert r = x"c8" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/blackbox01/testsuite.sh b/testsuite/synth/blackbox01/testsuite.sh new file mode 100755 index 000000000..9e5802045 --- /dev/null +++ b/testsuite/synth/blackbox01/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze blackbox1_adder.vhdl blackbox1.vhdl tb_blackbox1.vhdl +elab_simulate tb_blackbox1 +clean + +synth blackbox1.vhdl -e > syn_blackbox1.vhdl +analyze blackbox1_adder.vhdl syn_blackbox1.vhdl tb_blackbox1.vhdl +elab_simulate tb_blackbox1 +clean + +echo "Test successful" |