testsuite/synth/blackbox01/blackbox1_adder.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity blackbox1_adder is
  port (a, b : in std_logic_vector(7 downto 0);
        r : out std_logic_vector(7 downto 0));
end blackbox1_adder;

architecture behav of blackbox1_adder is
begin
  r <= std_logic_vector(unsigned(a) + unsigned(b));
end behav;