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author | Tristan Gingold <tgingold@free.fr> | 2019-09-04 06:52:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-04 06:52:35 +0200 |
commit | 4cb565baea6e93f804bef253200f0872428a3daa (patch) | |
tree | 6ed5ee76fe6c1c9e52d94a03666e1d121ccfd094 /testsuite/synth/dispin01 | |
parent | 95433bc986b16badf5a48ab00df861d0424ca983 (diff) | |
download | ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.gz ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.bz2 ghdl-4cb565baea6e93f804bef253200f0872428a3daa.zip |
testsuite/synth: rename disp01 to dispin01
Diffstat (limited to 'testsuite/synth/dispin01')
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec01.vhdl | 9 | ||||
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec02.vhdl | 9 | ||||
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec03.vhdl | 11 | ||||
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec04.vhdl | 9 | ||||
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec05.vhdl | 10 | ||||
-rw-r--r-- | testsuite/synth/dispin01/pkg_rec06.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/dispin01/rec01.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/dispin01/rec02.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/dispin01/rec03.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/dispin01/rec04.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/dispin01/rec05.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/dispin01/rec06.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/dispin01/tb_rec01.vhdl | 28 | ||||
-rw-r--r-- | testsuite/synth/dispin01/tb_rec02.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/dispin01/tb_rec03.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/dispin01/tb_rec04.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/dispin01/tb_rec05.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/dispin01/tb_rec06.vhdl | 39 | ||||
-rwxr-xr-x | testsuite/synth/dispin01/testsuite.sh | 16 |
19 files changed, 381 insertions, 0 deletions
diff --git a/testsuite/synth/dispin01/pkg_rec01.vhdl b/testsuite/synth/dispin01/pkg_rec01.vhdl new file mode 100644 index 000000000..c2048c3ea --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec01.vhdl @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + +package rec01_pkg is + type myrec is record + a : std_logic; + b : std_logic; + end record; +end rec01_pkg; diff --git a/testsuite/synth/dispin01/pkg_rec02.vhdl b/testsuite/synth/dispin01/pkg_rec02.vhdl new file mode 100644 index 000000000..5b5b78850 --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec02.vhdl @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + +package rec02_pkg is + type myrec is record + a : natural range 0 to 5; + b : std_logic; + end record; +end rec02_pkg; diff --git a/testsuite/synth/dispin01/pkg_rec03.vhdl b/testsuite/synth/dispin01/pkg_rec03.vhdl new file mode 100644 index 000000000..2c6204201 --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec03.vhdl @@ -0,0 +1,11 @@ +library ieee; +use ieee.std_logic_1164.all; + +package rec03_pkg is + type myenum is (s0, s1, s2, s3); + + type myrec is record + a : myenum; + b : std_logic; + end record; +end rec03_pkg; diff --git a/testsuite/synth/dispin01/pkg_rec04.vhdl b/testsuite/synth/dispin01/pkg_rec04.vhdl new file mode 100644 index 000000000..01cb4da3f --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec04.vhdl @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + +package rec04_pkg is + type myrec is record + a : std_logic_vector (3 downto 0); + b : std_logic; + end record; +end rec04_pkg; diff --git a/testsuite/synth/dispin01/pkg_rec05.vhdl b/testsuite/synth/dispin01/pkg_rec05.vhdl new file mode 100644 index 000000000..c73c67f05 --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec05.vhdl @@ -0,0 +1,10 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package rec05_pkg is + type myrec is record + a : unsigned (3 downto 0); + b : std_logic; + end record; +end rec05_pkg; diff --git a/testsuite/synth/dispin01/pkg_rec06.vhdl b/testsuite/synth/dispin01/pkg_rec06.vhdl new file mode 100644 index 000000000..9360a6a70 --- /dev/null +++ b/testsuite/synth/dispin01/pkg_rec06.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package rec06_pkg is + type myrec2 is record + c : natural range 2 to 3; + d : unsigned (3 downto 0); + end record; + + type myrec is record + a : myrec2; + b : std_logic; + end record; +end rec06_pkg; diff --git a/testsuite/synth/dispin01/rec01.vhdl b/testsuite/synth/dispin01/rec01.vhdl new file mode 100644 index 000000000..2d26098f8 --- /dev/null +++ b/testsuite/synth/dispin01/rec01.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.rec01_pkg.all; + +entity rec01 is + port (inp : myrec; + o : out std_logic); +end rec01; + +architecture behav of rec01 is +begin + o <= inp.a or inp.b; +end behav; diff --git a/testsuite/synth/dispin01/rec02.vhdl b/testsuite/synth/dispin01/rec02.vhdl new file mode 100644 index 000000000..ae82df551 --- /dev/null +++ b/testsuite/synth/dispin01/rec02.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.rec02_pkg.all; + +entity rec02 is + port (inp : myrec; + o : out std_logic); +end rec02; + +architecture behav of rec02 is +begin + o <= inp.b when inp.a > 3 else '0'; +end behav; diff --git a/testsuite/synth/dispin01/rec03.vhdl b/testsuite/synth/dispin01/rec03.vhdl new file mode 100644 index 000000000..f50e5eb09 --- /dev/null +++ b/testsuite/synth/dispin01/rec03.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.rec03_pkg.all; + +entity rec03 is + port (inp : myrec; + o : out std_logic); +end rec03; + +architecture behav of rec03 is +begin + o <= inp.b when inp.a = s2 else '1'; +end behav; diff --git a/testsuite/synth/dispin01/rec04.vhdl b/testsuite/synth/dispin01/rec04.vhdl new file mode 100644 index 000000000..3fab4012b --- /dev/null +++ b/testsuite/synth/dispin01/rec04.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.rec04_pkg.all; + +entity rec04 is + port (inp : myrec; + o : out std_logic); +end rec04; + +architecture behav of rec04 is +begin + o <= '1' when inp.a (1) = inp.b else '0'; +end behav; diff --git a/testsuite/synth/dispin01/rec05.vhdl b/testsuite/synth/dispin01/rec05.vhdl new file mode 100644 index 000000000..c9029fbb2 --- /dev/null +++ b/testsuite/synth/dispin01/rec05.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.rec05_pkg.all; + +entity rec05 is + port (inp : myrec; + o : out std_logic); +end rec05; + +architecture behav of rec05 is +begin + o <= '1' when inp.a (1) = inp.b else '0'; +end behav; diff --git a/testsuite/synth/dispin01/rec06.vhdl b/testsuite/synth/dispin01/rec06.vhdl new file mode 100644 index 000000000..5e6b4ae45 --- /dev/null +++ b/testsuite/synth/dispin01/rec06.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.rec06_pkg.all; + +entity rec06 is + port (inp : myrec; + o : out std_logic); +end rec06; + +architecture behav of rec06 is +begin + o <= inp.b when inp.a.d > inp.a.c else '0'; +end behav; diff --git a/testsuite/synth/dispin01/tb_rec01.vhdl b/testsuite/synth/dispin01/tb_rec01.vhdl new file mode 100644 index 000000000..fbfda0a7e --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec01.vhdl @@ -0,0 +1,28 @@ +entity tb_rec01 is +end tb_rec01; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec01_pkg.all; + +architecture behav of tb_rec01 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec01 + port map (inp => inp, o => r); + + process + constant av : std_logic_vector := b"11001"; + constant bv : std_logic_vector := b"01011"; + constant rv : std_logic_vector := b"11011"; + begin + for i in av'range loop + inp.a <= av (i); + inp.b <= bv (i); + wait for 1 ns; + assert r = rv(i) severity failure; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/dispin01/tb_rec02.vhdl b/testsuite/synth/dispin01/tb_rec02.vhdl new file mode 100644 index 000000000..18b326047 --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec02.vhdl @@ -0,0 +1,39 @@ +entity tb_rec02 is +end tb_rec02; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec02_pkg.all; + +architecture behav of tb_rec02 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec02 + port map (inp => inp, o => r); + + process + begin + inp.a <= 5; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= 2; + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= 1; + inp.b <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= 4; + inp.b <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dispin01/tb_rec03.vhdl b/testsuite/synth/dispin01/tb_rec03.vhdl new file mode 100644 index 000000000..7495ac183 --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec03.vhdl @@ -0,0 +1,39 @@ +entity tb_rec03 is +end tb_rec03; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec03_pkg.all; + +architecture behav of tb_rec03 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec03 + port map (inp => inp, o => r); + + process + begin + inp.a <= s0; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= s2; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= s2; + inp.b <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= s3; + inp.b <= '0'; + wait for 1 ns; + assert r = '1' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dispin01/tb_rec04.vhdl b/testsuite/synth/dispin01/tb_rec04.vhdl new file mode 100644 index 000000000..3dba996da --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec04.vhdl @@ -0,0 +1,39 @@ +entity tb_rec04 is +end tb_rec04; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec04_pkg.all; + +architecture behav of tb_rec04 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec04 + port map (inp => inp, o => r); + + process + begin + inp.a <= "0000"; + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= "0010"; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= "1101"; + inp.b <= '0'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= "1101"; + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dispin01/tb_rec05.vhdl b/testsuite/synth/dispin01/tb_rec05.vhdl new file mode 100644 index 000000000..a751767e8 --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec05.vhdl @@ -0,0 +1,39 @@ +entity tb_rec05 is +end tb_rec05; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec05_pkg.all; + +architecture behav of tb_rec05 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec05 + port map (inp => inp, o => r); + + process + begin + inp.a <= "0000"; + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= "0010"; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= "1101"; + inp.b <= '0'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= "1101"; + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dispin01/tb_rec06.vhdl b/testsuite/synth/dispin01/tb_rec06.vhdl new file mode 100644 index 000000000..d46d64d18 --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec06.vhdl @@ -0,0 +1,39 @@ +entity tb_rec06 is +end tb_rec06; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec06_pkg.all; + +architecture behav of tb_rec06 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec06 + port map (inp => inp, o => r); + + process + begin + inp.a <= (2, "0000"); + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= (2, "0110"); + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= (3, "1001"); + inp.b <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= (3, "0001"); + inp.b <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dispin01/testsuite.sh b/testsuite/synth/dispin01/testsuite.sh new file mode 100755 index 000000000..74df646f9 --- /dev/null +++ b/testsuite/synth/dispin01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in rec01 rec02 rec03 rec04 rec05 rec06; do + analyze pkg_$t.vhdl $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth pkg_$t.vhdl $t.vhdl -e $t > syn_$t.vhdl + analyze pkg_$t.vhdl syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |