| Commit message (Expand) | Author | Age | Files | Lines |
* | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 |
* | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 |
* | Remove debug | Eddie Hung | 2019-07-22 | 1 | -1/+0 |
* | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 1 | -0/+1 |
* | opt and wreduce necessary for -dsp | Eddie Hung | 2019-07-22 | 1 | -2/+4 |
* | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 |
* | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 2 | -9/+10 |
* | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 |
* | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
* | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
* | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 |
* | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
|\ |
|
| * | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 15 | -84/+164 |
| |\ |
|
* | \ | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 3 | -7/+239 |
|\ \ \ |
|
| * | | | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 |
| * | | | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 |
| * | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 |
| * | | | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 |
| * | | | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
| | |/
| |/| |
|
* | | | Use sign_headroom instead | Eddie Hung | 2019-07-19 | 1 | -4/+4 |
* | | | Fix SB_MAC sim model -- do not sign extend internal products? | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
* | | | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 |
* | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 1 | -33/+18 |
|\| | |
|
| * | | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 |
| |\ \ |
|
| | * | | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 |
| | * | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 |
| | * | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 |
| | * | | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 1 | -28/+10 |
| | * | | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | * | | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| * | | | synth_intel: rename for consistency with #1184 | Dan Ravensloft | 2019-07-18 | 1 | -4/+4 |
| |/ / |
|
* | | | Do not define `DSP_SIGNEDONLY macro if no exists | Eddie Hung | 2019-07-18 | 1 | -4/+3 |
* | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 14 | -51/+146 |
|\| | |
|
| * | | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 |
| |\ \ |
|
| | * | | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 |
| | * | | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 2 | -5/+9 |
| * | | | Merge pull request #1204 from smunaut/fix_1187 | David Shah | 2019-07-17 | 2 | -4/+4 |
| |\ \ \ |
|
| | * | | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 |
| * | | | | gen_lut to return correctly sized LUT mask | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
| |/ / / |
|
| * | | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 8 | -29/+120 |
| |\ \ \
| | |/ /
| |/| | |
|
| | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 7 | -8/+8 |
| | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT | Eddie Hung | 2019-07-13 | 1 | -9/+7 |
| | * | | Use Const::from_string() not its constructor... | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
| | * | | Off by one | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
| | * | | Fix spacing | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
| | * | | Remove double push | Eddie Hung | 2019-07-12 | 1 | -1/+0 |
| | * | | Map to and from this box if -abc9 | Eddie Hung | 2019-07-12 | 1 | -2/+3 |
| | * | | ice40_opt to handle this box and opt back to SB_LUT4 | Eddie Hung | 2019-07-12 | 1 | -0/+48 |
| | * | | Add new box to cells_sim.v | Eddie Hung | 2019-07-12 | 1 | -2/+25 |