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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 15:50:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 15:50:13 -0700 |
| commit | 595a8f032f1e9db385959f92a4a414a40de291fd (patch) | |
| tree | 9865331e29ff6676c1a326298dcf44a9eb680771 /techlibs | |
| parent | e87916b7eb7dd9fccaab19f7d494f44bdfb929f5 (diff) | |
| download | yosys-595a8f032f1e9db385959f92a4a414a40de291fd.tar.gz yosys-595a8f032f1e9db385959f92a4a414a40de291fd.tar.bz2 yosys-595a8f032f1e9db385959f92a4a414a40de291fd.zip | |
Do not do sign extension in techmap; let packer do it
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 5444d842a..70c2c42c6 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -196,24 +196,15 @@ module \$__mul (A, B, Y); assign Y = partial_sum[n-1];
end
else begin
- if (A_SIGNED)
- wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
- else
- wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
- if (B_SIGNED)
- wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
- else
- wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
-
`DSP_NAME #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
- .A_WIDTH(`DSP_A_MAXWIDTH),
- .B_WIDTH(`DSP_B_MAXWIDTH),
- .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)),
) _TECHMAP_REPLACE_ (
- .A(Aext),
- .B(Bext),
+ .A(A),
+ .B(B),
.Y(Y)
);
end
|