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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 21:03:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 21:03:54 -0700 |
| commit | bddd641290d3c01d86144362cd0e16c82e0bcfd8 (patch) | |
| tree | 7f385d4d484cbfb666771891989df79f8b7ef82a /techlibs | |
| parent | 601fac97e4c48d524d5c7f9b4688b536c2e1c891 (diff) | |
| download | yosys-bddd641290d3c01d86144362cd0e16c82e0bcfd8.tar.gz yosys-bddd641290d3c01d86144362cd0e16c82e0bcfd8.tar.bz2 yosys-bddd641290d3c01d86144362cd0e16c82e0bcfd8.zip | |
Fix SB_MAC sim model -- do not sign extend internal products?
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 609facc93..4402f8d36 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1363,9 +1363,9 @@ module SB_MAC16 ( wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl; wire [15:0] Ah, Al, Bh, Bl; assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]}; - assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; + assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]}; - assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; + assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; assign p_Ah_Bh = Ah * Bh; assign p_Al_Bh = Al * Bh; assign p_Ah_Bl = Ah * Bl; |