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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 00:53:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 00:53:01 -0700 |
| commit | 62ac5ebd02e18add18a11f4c19002f4059b091b7 (patch) | |
| tree | a4b4cc27a3c81057e8ecdb8839df4839aae60cab /techlibs | |
| parent | 0f5bddcd792ed2da2b9a3eb12e775537f394e771 (diff) | |
| download | yosys-62ac5ebd02e18add18a11f4c19002f4059b091b7.tar.gz yosys-62ac5ebd02e18add18a11f4c19002f4059b091b7.tar.bz2 yosys-62ac5ebd02e18add18a11f4c19002f4059b091b7.zip | |
Map to and from this box if -abc9
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2c75215cb..59f6d1863 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -242,7 +242,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -D_ABC +/ice40/cells_sim.v"); + run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -298,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass if (nocarry) run("techmap"); else - run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); + run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : "")); if (retime || help_mode) run(abc + " -dff", "(only if -retime)"); run("ice40_opt"); @@ -342,6 +342,7 @@ struct SynthIce40Pass : public ScriptPass else wire_delay = 250; run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); |