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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 21:02:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 21:02:49 -0700 |
| commit | 601fac97e4c48d524d5c7f9b4688b536c2e1c891 (patch) | |
| tree | 90e663a35a1452015caefd8ed58ce0265688d4c5 /techlibs | |
| parent | a777be30913105c3685417738f90f635ba7a3b62 (diff) | |
| download | yosys-601fac97e4c48d524d5c7f9b4688b536c2e1c891.tar.gz yosys-601fac97e4c48d524d5c7f9b4688b536c2e1c891.tar.bz2 yosys-601fac97e4c48d524d5c7f9b4688b536c2e1c891.zip | |
Add params
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 32f570935..3d7b09d69 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,10 @@ module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + wire [47:0] P_48; DSP48E1 #( // Disable all registers |