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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 01:08:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 01:08:48 -0700 |
| commit | 4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8 (patch) | |
| tree | 77356bb46d5bc10aa146a683623dbe5df94c2888 /techlibs | |
| parent | 62ac5ebd02e18add18a11f4c19002f4059b091b7 (diff) | |
| download | yosys-4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8.tar.gz yosys-4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8.tar.bz2 yosys-4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8.zip | |
Remove double push
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index b22fc83fe..4e50b250e 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -117,7 +117,6 @@ static void run_ice40_opts(Module *module) log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "\\SB_LUT4"; - sb_lut_cells.push_back(cell); cell->setPort("\\I0", RTLIL::S0); cell->setPort("\\I1", inbit[0]); cell->setPort("\\I2", inbit[1]); |