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* Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
* Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
* Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
* Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| * Fix typo in BEddie Hung2019-07-191-1/+1
| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
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* | \ Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| * | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| * | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| * | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
| * | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
* | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
* | | Add paramsEddie Hung2019-07-181-0/+6
* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| | * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| | * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| | * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| * | | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
* | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1814-51/+146
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| * | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
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| | * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| | * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
| * | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
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| | * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| * | | | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
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| | * | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
| | * | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
| | * | Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
| | * | Off by oneEddie Hung2019-07-121-1/+1
| | * | Fix spacingEddie Hung2019-07-121-1/+1
| | * | Remove double pushEddie Hung2019-07-121-1/+0
| | * | Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
| | * | ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
| | * | Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
| | * | _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
| | * | Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
* | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
* | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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* | | Make consistentEddie Hung2019-07-181-1/+2
* | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
* | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
* | | Working for unsignedEddie Hung2019-07-181-52/+28
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